Wafer Level Chip Scale Package Interconnects and Methods of Manufacture Thereof

ABSTRACT

A method of forming a wafer level chip scale package interconnect may include: forming a post-passivation interconnect (PPI) layer over a substrate; forming an interconnect over the PPI layer; and releasing a molding compound material over the substrate, the molding compound material flowing to laterally encapsulate a portion of the interconnect.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications,such as personal computers, cell phones, digital cameras, and otherelectronic equipment, as examples. Semiconductor devices are typicallyfabricated by sequentially depositing insulating or dielectric layers,conductive layers, and semiconductor layers of material over asemiconductor substrate, and patterning the various material layersusing lithography to form circuit components and elements thereon.

Interconnects may be formed to join two substrates. An array ofinterconnects may be deposited on the bonding pads of a first substrate,with a second substrate joined at its own bonding pad sites to the firstsubstrate via the interconnects. For example, interconnects may besolder balls formed on a pad and then reflowed to attach a secondsubstrate. The interconnects may be formed with a layout different fromthe land layout to permit customization of the output layout. This maybe accomplished with metal lines disposed in a dielectric, with one ormore metal layers overlying the lands and connected to the lands byconductive plating layers.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A to 1G show a process flow illustrating some of the steps of amethod for forming an interconnect, in accordance with some embodiments.

FIG. 2 shows a top-down view of a substrate and a dam ring formed alongan edge of the substrate, in accordance with some embodiments.

FIG. 3 shows an enlarged view of the interconnect shown in FIG. 1G, inaccordance with some embodiments.

FIG. 4 shows a top-down view of a plurality of interconnects formed overa substrate, in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and stacks are described belowto simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

FIGS. 1A to 1G show a process flow illustrating some of the steps of amethod for forming an interconnect, in accordance with an embodiment.FIG. 1A shows a substrate 102 having a first surface 102 a and a secondsurface 102 b opposite the first surface 102 a. The substrate 102 may bewafer, a chip, a die, a package, or the like. As an example, thesubstrate 102 may be a wafer level chip scale package (WLCSP) structure.The substrate 102 may comprise a semiconductive material. As examples,the substrate 102 may comprise an elementary semiconductor (e.g.including silicon and/or germanium in crystal), a compound semiconductor(e.g. including at least one of silicon carbide, gallium arsenic,gallium phosphide, indium phosphide, indium arsenide, or indiumantimonide), an alloy semiconductor (e.g. including at least one ofSiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP), or combinationsthereof.

The substrate 102 may have one or more devices (e.g. active and/orpassive devices) formed therein or thereon. The one or more devices arenot shown in FIG. 1A for the sake of simplicity. The one or more devicesformed in or on the substrate 102 may be electrically connected to oneor more contact pads 104 that may be disposed over the first surface 102a of the substrate 102. Only one contact pad 104 is shown as an example;however, more than one contact pad 104 may be disposed over the firstsurface 102 a of the substrate 102. The one or more contact pads 104 maycomprise a conductive material. As an example, the one or more contactpads 104 may comprise aluminum (Al), polysilicon, gold (Au), copper(Cu), tantalum (Ta), tungsten (W), silver (Ag), palladium (Pd),combinations thereof, or the like.

FIG. 1B shows a first insulating layer 106 formed over the substrate102, e.g. to passivate the first surface 102 a of the substrate 102. Thefirst insulating layer 106 may have one or more openings 108 that mayexpose at least a portion of the one or more contact pads 104. In anembodiment, the first insulating layer 106 may be a substantiallyconformal layer. The first insulating layer 106 may be formed bychemical vapor deposition (CVD), physical vapor deposition (PVD), atomiclayer deposition (ALD), a spin-on-dielectric process, combinationsthereof, or the like. The one or more openings 108 may be formed byetching portions of the first insulating layer 106 disposed over the oneor more contact pads 104, e.g. using a photolitographic etching process.The first insulating layer 104 may comprise a dielectric material. As anexample, the first insulating layer 104 may comprise silicon oxide,silicon dioxide (SiO₂), silicon nitride (SiN), silicon carbide (SiC),titanium nitride (TiN), combinations thereof, or the like.

FIG. 1C shows a second insulating layer 110 formed over the firstinsulating layer 106. The second insulating layer 110 and the firstinsulating layer 106 may differ in composition. As an example, thesecond insulating layer 110 may comprise a polymer, examples of whichinclude a polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO),combinations thereof, or the like. In an embodiment, the secondinsulating layer 110 may be a substantially conformal layer. The secondinsulating layer 110 may be formed using similar process as describedabove in respect of the first insulating layer 106. In the example shownin FIG. 1C, the second insulating layer 110 may cover sidewalls of theone or more openings 108. However, in another example, the secondinsulating layer 110 may be disposed (e.g. fully disposed) outside theone or more openings 108 and over a surface of the first insulatinglayer 106 facing away from the substrate 102.

FIG. 1D shows a post-passivation interconnect (PPI) layer 112 formedover the one or more contact pads 104 and the second insulating layer110. The PPI layer 112 may comprise a contact portion 112 a disposedwithin the one or more openings 108 and an extension portion 112 bdisposed outside the one or more openings 108 and extending over thesecond insulating layer 110. The PPI layer 112 may be a conductivelayer, such as a metal layer, formed to extend from the one or morecontact pads 104 to a region over the second insulating layer 110. ThePPI layer 112 may be formed by blanket deposition of a metal layer andsubsequent masking and etching of the metal layer. The PPI layer 112 mayalso be formed by depositing a mask and then depositing a metal in themask openings to form a PPI layer 112. The PPI layer 112 may be formedwith a thickness between about 4 μm and about 10 μm. In an embodiment,the PPI layer 112 may be copper or another conductive material, such asgold, aluminum, silver, tungsten, palladium, or another metal, alloy orthe like. The PPI layer 112 may be deposited using a vapor depositionmethod such as molecular beam epitaxy (MBE), chemical vapor deposition(CVD) or plasma enhanced CVD (PECVD), or by electroplating, atomic layerdeposition (ALD), or the like. Forming the PPI layer 112 may alsocomprise forming an initial barrier layer, seed layer or the like, andforming the PPI layer 112 over the initial layer. In such an embodiment,the seed layer may be formed, then a mask applied, and the PPI layer 112deposited via electroplating. The mask and any excess seed layer may besubsequently removed.

FIG. 1E shows an interconnect 114 formed over the PPI layer 112, e.g.over the extension portion 112 b of the PPI layer 112. The interconnect114 may comprise a conductive material such as gold, copper, aluminum,lead (Pb), silver, tungsten, tin (Sn), a solder paste, a conductiveepoxy or polymer, combinations thereof, or the like. The interconnect114 may be formed over the PPI layer 112 by deposition, evaporation,electroplating, printing, solder transfer, a combination thereof, or thelike. In some embodiments, the interconnect 114 may be a solder bump.

FIG. 1F shows the formation of dam members 116 over the secondinsulating layer 110. The dam members 116 may be laterally separatedfrom the PPI layer 112. In an embodiment where the substrate 102 is awafer, the dam members 116 may be a part of a ring that may be formedalong an edge of the substrate 102. As an example, FIG. 2 shows atop-down view of a dam ring 216 formed along an edge of the substrate102. The dam members 116 shown in FIG. 1F may, as an example, be across-sectional view of the dam ring 216 taken along a line A-A′ shownin FIG. 2. The dam members 116 may comprise a polyimide, polybenzoxazole(PBO), benzocyclobutene (BCB), silicones, acrylates, polymers, epoxy,and the like, although other relatively soft, often organic, dielectricmaterials can also be used. As an example, the dam members 116 maycomprise a material having a coefficient of thermal expansion (CTE) inthe range from about 10 ppm/K to about 250 ppm/K, a Young's Modulus inthe range from about 0.05 GPa to 4.5 GPa, and a glass transitiontemperature (Tg) in the range from about −10 degrees Celsius to about450 degrees Celsius. In some embodiments, the dam members 116 may have adimension D1 (e.g. a height) which may be in a range from about 30micrometers to about 80 micrometers (e.g. about 50 micrometers).

The dam members 116 may be formed by photolithography in which amaterial for the dam members 116 is deposited over the second insulatinglayer 110 and the PPI layer 112, patterned, and then etched to form thedam members 116. In some embodiments, the dam members 116 may be formedby a printing method. Using the printing method, a stencil with openingsmay be overlaid on the second insulating layer 110 and the PPI layer112. Subsequently, material for the dam members 116 may be dispensedover the stencil. In some embodiments, one or more blades or wipers maybrush across the stencil back and forth to apply the material into theopenings of the stencil. In some other embodiments, the dam members 116may be formed by a taping method. In one embodiment, a tape havingpre-formed dam members 116 may be applied to the second insulating layer110 and the PPI layer 112. The tape may then be removed to leave behindthe dam members 116.

FIG. 1G shows a third insulating layer 118 formed over the PPI layer112. The third insulating layer 118 may comprise an oxide, a nitride, ora polymer such as a polyimide, a polybenzoxazole (PBO), benzocyclobutene(BCB), an epoxy, a liquid molding compound, a resin, a moldable polymer,or the like. As shown in FIG. 1G, the third insulating layer 118 may beformed by releasing molding compound material 120 using a dispenser 122.The molding compound material 120 may be released using a dispensingand/or printing process. In some embodiments, the dispenser 122 may bepositioned near an edge region of the substrate 102, which may be aregion of the substrate 102 in which the dam members 116 are formed. Asmolding compound material 120 for the third insulating layer 118 isdispensed and/or printed (e.g. using an ink-jet), the molding compoundmaterial 120 may flow across the PPI layer 112 and may at leastlaterally encapsulate the PPI layer 112. Portions of the interconnect114 proximal the substrate 102 may also be surrounded by the thirdinsulating layer 118. In some embodiments, the dam members 116 mayfunction to prevent spillage of the third insulating layer 118 such thatthe molding compound material 120 of the third insulating layer 118 iscontained within a lateral extent L1 of the substrate 102. The processflow may continue with a curing of the third insulating layer 118. Thecuring process may include a first stage of heating the third insulatinglayer 118 from about room temperature to a first temperature that may begreater than about 100 degrees Celsius (e.g. in a range from about 100degrees Celsius to about 140 degrees Celsius). The first temperature maybe held for a duration of at least about 20 minutes. Following this, asecond stage of the curing process may include heating the thirdinsulating layer 118 from the first temperature to a second temperaturethat may be in a range from about 150 degrees Celsius to about 400degrees Celsius. The second temperature may subsequently be held for aduration of at least 20 minutes.

The third insulating layer 118 may comprise a material having a CTEgreater than about 3 ppm/K, e.g. in the range from about 10 ppm/K toabout 250 ppm/K. The third insulating layer 118 may comprise fillerparticles, such as silica filler, glass filler or similar fillers. Adimension of each of the filler particles (e.g. a width) may be lessthan about 5 micrometers. The filler particles may make up less than 10percent by weight of the third insulating layer 118. As a result of theCTE of the third insulating layer 118, the size of the filler particlesin the third insulating layer 118, and/or the proportion, by weight, ofthe filler particles in the third insulating layer 118, the moldingcompound material 120 may be dense and may have a high viscosity,thereby allowing for greater control of a thickness of the thirdinsulating layer 118. Furthermore, as a result of the greater density ofthe third insulating layer 118 (e.g. compared to the first and secondinsulating layers 106, 110), the thickness of the third insulating layer118 may be reduced while still the necessary mechanical protection tothe underlying conductive and/or non-conductive layers. Even further,the greater control of a thickness of the third insulating layer 118can, in turn, result in a substantially uniform thickness of the thirdinsulating layer 118 along the lateral extent L1 of the substrate 102.

The process flow shown in FIGS. 1A to 1G utilizes a printing and/ordispensing process to form the third insulating layer 118. The printingand/or dispensing process is possible due, at least in part, to thegreater density of the third insulating layer 118 (e.g. compared to thefirst and second insulating layers 106, 110). Furthermore, the printingand/or dispensing process can be implemented using simple steps andsimple equipment, e.g. compared to other techniques for forming thethird insulating layer 118 such as compression molding processes thatmay be followed by a plasma clean process. This can lead to significantcost reductions. For example, the printing and/or dispensing process maybe accomplished by an inkjet printer, which is cheaper than a moldingtool that may be used in a compression molding process. Furthermore,using a printing and/or dispensing process to form the third insulatinglayer 118 can lead to high manufacturing throughput, e.g. compared toother techniques for forming the third insulating layer 118 such ascompression molding processes that may be followed by a plasma cleanprocess. Even further, as shown in FIGS. 1A to 1G, no etch process isperformed in connection with the formation of the third insulating layer118. As such, substantially no residue material (e.g. organic and/orinorganic residue material) is formed on exposed surfaces of theinterconnect 114, which can lead to greater reliability of devices thatmay be manufactured using the process flow shown in FIGS. 1A to 1G.

FIG. 3 shows an enlarged view of the interconnect shown in FIG. 1G, inaccordance with an embodiment. In essence, FIG. 3 shows the thirdinsulating layer 118 overlying the PPI layer 112 and covering a lowerportion of the interconnect 114. A top surface of the third insulatinglayer 118 has a concave surface region and a planar surface region, theconcave surface region being positioned between the solder bump and theplanar surface region as shown in FIG. 3, the concave surface regionextends outwards from the interconnect 114.

As shown in FIG. 3, the third insulating layer 118 may laterallysurround a portion the interconnect 114 (e.g. the lower portion of theinterconnect 114). The third insulating layer 118 may physically contactthe interconnect 114 at a waist W of the interconnect 114. As shown inFIG. 3, the third insulating layer 118 may have a curved surface aroundthe interconnect 114, e.g. as a result of the third insulating layer 118climbing to the waist W of the interconnect 114. As an example, thethird insulating layer 118 may have a concave surface extending outwardsfrom the interconnect 114. Due to the high density and viscosity of thethird insulating layer 118, the curved surface of the third insulatinglayer 118 shows a steep drop off since the third insulating layer 118does not climb over a substantial portion of the interconnect 114. As anexample, an angle φ subtended between an axis parallel to the firstsurface 102 a of the substrate 102 and a tangent to the waist W of thethird insulating layer 118 may less than about 100 degrees. FIG. 3 alsoshows the interconnect 114 having a total height H1, of which height H2is exposed. In an embodiment, the height H2 may be at least 30 percent(e.g. greater than about 50 percent) of the total height H1 of theinterconnect 114 since the third insulating layer 118 does not climbover a substantial portion of the interconnect 114. As a result, astand-off height of the interconnect 114 is increases, e.g. compared toother techniques for forming the third insulating layer 118 such ascompression molding processes that may be followed by a plasma cleanprocess. In some embodiments, a thickness H3 of the third insulatinglayer 118 over the PPI layer 112 may be in a range from about 0.1micrometers to about 10 micrometers, while the total height H1 of theinterconnect 114 may be in a range from about 100 micrometers to about250 micrometers.

FIG. 4 shows a top-down view of a plurality of interconnects 414-1,414-2 formed over the substrate 102. The plurality of interconnects414-1, 414-2 may be arranged as an array of interconnects, as shown inthe example of FIG. 4. Other features such as the one or more contactpads 104, the first insulating layer 106, the second insulating layer110, and the PPI layer 112 are not shown in FIG. 4 for the sake ofsimplicity. The plurality of interconnects 414-1, 414-2 may comprisecorner interconnects 414-1 that may be disposed at corner regions of thesubstrate 102. The plurality of interconnects 414-1, 414-2 may alsocomprise central interconnects 414-2 that may be disposed in centralregions of the substrate 102. As described above, the process flow shownin FIGS. 1A to 1G can result in an increased stand-off height of theinterconnect 114. Similarly, the process flow shown in FIGS. 1A to 1Gmay be used to form the third insulating layer 118 around each of theplurality of interconnects 414-1, 414-2. However, in another embodiment,instead of forming the third insulating layer 118 around each of theplurality of interconnects 414-1, 414-2, the dispensing and/or printingprocess described above may be used to form the third insulating layer118 around selected ones of the plurality of interconnects 414-1, 414-2.As an example, it may be desirable to decrease a thickness of the thirdinsulating layer 118 at corners regions of the substrate 102 compared tocentral regions thereof in order to increase interconnect stand-offheight at the corner regions of the substrate 102 so as to improveon-board reliability. As an example, it may be desirable that the thirdinsulating layer 118 located at central regions of the substrate 102(e.g. located around central interconnects 414-2) be at least about 5micrometers thicker than the third insulating layer 118 located atcorner regions of the substrate 102 (e.g. located around cornerinterconnects 414-1). This difference in thicknesses of the thirdinsulating layer 118 at different regions of the substrate 102 may beaccomplished by using the process flow shown in FIGS. 1A to 1G toselectively dispense and/or print the third insulating layer 118 aroundthe corner interconnects 414-1 so as to prevent the third insulatinglayer 118 from climbing over a substantial portion of the cornerinterconnects 414-1. As described above, this may, in turn, increaseinterconnect stand-off height and improve on-board reliability. Itshould be noted, however, that the thicknesses of the insulating layer118 between adjacent (e.g. immediately adjacent) central interconnects414-2 may be substantially equal to the thickness of the insulatinglayer 118 between a central interconnect 414-2 and the edge of thesubstrate 102.

In accordance with an embodiment, a method of forming a wafer level chipscale package interconnect may include: forming a post-passivationinterconnect (PPI) layer over a substrate; forming an interconnect overthe PPI layer; and releasing a molding compound material over thesubstrate, the molding compound material flowing to laterallyencapsulate a portion of the interconnect.

In accordance with an embodiment, a method of forming a wafer level chipscale package interconnect may include: forming a contact pad over asubstrate; forming a first insulating layer over the substrate and overa periphery of the contact pad, the first insulating layer having anopening exposing a central region of the contact pad; forming a secondinsulating layer over the first insulating layer; forming apost-passivation interconnect (PPI) layer over the second insulatinglayer, the PPI having a portion disposed in the opening and contactingthe contact pad; forming an interconnect over the PPI layer disposedover the second insulating layer; and forming a third insulating layerover the PPI layer using at least one of a printing or dispensingprocess, the third insulating layer laterally surrounding a portion ofthe interconnect proximal the substrate.

In accordance with an embodiment, a semiconductor package may include: asubstrate; a contact pad overlying the substrate; at least oneinsulating layer disposed over the substrate and having an openingexposing a portion of the contact pad; a post-passivation interconnect(PPI) layer disposed within the opening and extending over a surface ofthe at least one insulating layer facing away from the substrate; anarray of solder bumps overlying the PPI layer; and a molding compoundlayer overlying the PPI layer and covering a lower portion of eachsolder bump of the array of solder bumps, wherein a thickness of themolding compound surrounding a first solder bump located in a cornerregion of the substrate is less than a thickness of the molding compoundsurrounding a second solder bump located in a central region of thesubstrate.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

In the claims:
 1. A method, comprising: forming a post-passivationinterconnect (PPI) layer over a substrate; forming an interconnect overthe PPI layer; forming dam members over the substrate, the dam membersforming a ring surrounding the PPI layer; and releasing a moldingcompound material over the substrate, the molding compound materialflowing to laterally encapsulate a portion of the interconnect, themolding compound material having a greater thickness at a central regionwithin the ring than at a location proximate the ring.
 2. The method ofclaim 1, wherein the releasing the molding compound material comprisesat least one of a dispensing or a printing process.
 3. The method ofclaim 1, wherein the forming the PPI layer comprises at least one ofmolecular beam epitaxy, chemical vapor deposition, plasma enhancedchemical vapor deposition, electroplating, or atomic layer deposition.4. The method of claim 1, further comprising curing the molding compoundmaterial.
 5. The method of claim 1, wherein the molding compoundmaterial comprises at least one of a polybenzoxazole (PBO),benzocyclobutene (BCB), an epoxy, a liquid molding compound, a resin, ora moldable polymer.
 6. The method of claim 1, wherein the moldingcompound material comprises filler particles.
 7. The method of claim 6,wherein a dimension of the filler particles is less than about 5micrometers.
 8. The method of claim 6, wherein the filler particles makeup less than about 10 percent by weight of the molding compoundmaterial.
 9. The method of claim 1, wherein less than 5o percent of theinterconnect is laterally encapsulated by the molding compound material.10. A method, comprising: forming a contact pad over a substrate;forming a first insulating layer over the substrate and over a peripheryof the contact pad, the first insulating layer having an openingexposing a central region of the contact pad; forming a secondinsulating layer over the first insulating layer; forming apost-passivation interconnect (PPI) layer over the second insulatinglayer, the PPI having a portion disposed in the opening and contactingthe contact pad; forming an interconnect over the PPI layer disposedover the second insulating layer; and forming a third insulating layerover the PPI layer using at least one of a printing or dispensingprocess, the third insulating layer laterally surrounding a portion ofthe interconnect proximal the substrate, the third insulating layercontacting the portion at a waist of the interconnect, an anglesubtended between a tangent to the waist of the interconnect and an axisparallel to a major surface of the substrate is less than about 100degrees.
 11. The method of claim 10, further comprising: prior toforming the third insulating layer, forming dam members laterallyseparated from the PPI layer.
 12. The method of claim ii, wherein theforming the dam members comprises at least one of photolithography,taping, or printing.
 13. The method of claim 10, wherein the forming theinterconnect over the PPI layer comprises at least one of deposition,evaporation, electroplating, printing, or solder transfer.
 14. Themethod of claim 10, wherein a thickness of the third insulating layerover the PPI layer is in a range from about 0.1 micrometers to about 10micrometers.
 15. (canceled)
 16. A semiconductor package, comprising: asubstrate; a contact pad overlying the substrate; at least oneinsulating layer disposed over the substrate and having an openingexposing a portion of the contact pad; a post-passivation interconnect(PPI) layer disposed within the opening and extending over a surface ofthe at least one insulating layer facing away from the substrate; afirst solder bump and a second solder bump overlying the PPI layer; anda molding compound layer overlying the PPI layer and covering a lowerportion of each of the first solder bump and the second solder bump,wherein a thickness of the molding compound layer surrounding the firstsolder bump located in a corner region of the substrate is less than athickness of the molding compound layer surrounding the second solderbump located in a central region of the substrate.
 17. The semiconductorpackage of claim 16, wherein the thickness of the molding compound layersurrounding the second solder bump is at least about 5 micrometersgreater than the thickness of the molding compound layer surrounding thefirst solder bump.
 18. The semiconductor package of claim 16, wherein athickness of the molding compound layer between the second solder bumpand an edge of the substrate is substantially equal to a thickness ofthe molding compound layer between the second solder bump and a thirdsolder bump located in the central region of the substrate.
 19. Thesemiconductor package of claim 16, wherein less than 5o percent of thefirst solder bump is covered by the molding compound layer.
 20. Thesemiconductor package of claim 16, wherein the molding compound layerhas a coefficient of thermal expansion greater than about 3 ppm/K. 21.The method of claim 1, wherein the molding compound material contacts awaist of the interconnect, the waist being a portion of the interconnectproximate to the substrate, a tangent line at the waist of theinterconnect forming an angle of less than 100 degrees with an axisparallel to a major surface of the substrate.